The invention relates to a method for forming a semiconductor heterostructure comprising providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2, and providing a top layer over the buffer layer. The invention furthermore relates to the corresponding semiconductor heterostructure and to a semiconductor device that includes such semiconductor heterostructure.
Semiconductor heterostructures like this are known from U.S. Pat. No. 5,442,205, which discloses semiconductor heterostructure devices with strained semiconductor layers. The known heterostructure includes a strained epitaxial layer of silicon or germanium which is located over a silicon substrate with a spatially graded GexSi1-x epitaxial layer, which in turn is overlaid by an ungraded capping layer Gex0Si1-x0, intervening between the silicon substrate and the strained layer. The graded layer and the capping layer therein play the role of the buffer layer and the strained layer the role of the top layer. Such heterostructures can serve, for instance, as a foundation for surface emitting LEDs or MOS FETs.
The spatially graded GexSi1-x layer of the buffer layer is used to adapt the lattice parameter between the underlying substrate and the deposited relaxed material, while trying to minimize the density of defects. Usually the additional capping layer of SiGe with constant Ge concentration corresponding to the concentration obtained at the top of the graded layer is provided as a relaxed layer to improve the crystalline quality of the structure.
The structure obtained usually has a surface morphology that is not suitable for further use. US patent application 2003/0215990, which is preoccupied by preventing interdiffusion of dopants in semiconductor heterostructures, proposes a planarization step, in particular a Chemical Mechanical Polishing (CMP) step, before growing any further layer(s). Here it is the role of CMP to provide a polished smooth surface, which is typically of about 2 Å. Following CMP, the substrate needs to be further treated to prepare the subsequent layer deposition. Such treatments include treating the surface using a HF solution and furthermore a bake to remove any oxide. Then, the 2003/0215990 application proposes epitaxial deposition of further layers like silicon germanium or strained silicon layers.
It appears, however, that the achieved surface properties for the semiconductor heterostructures are not completely acceptable when applying the above described prior art processes. Indeed, due to the heat treatment or bake that is applied prior to the deposition of the further layers, a roughening of the silicon germanium surface occurs. During the subsequent growth of, e.g., a strained silicon layer, the surface roughness tends to diminish again the final roughness, but nevertheless stays considerably higher than the roughness of the graded GeSi layer surface or of the capping layer, if present, after completing the CMP process. As the thickness of the strained silicon layer cannot exceed the critical thickness, beyond which defects would nucleate within the layer or at the interface of the strained and the underlying layers, this roughness can lead to defects. When the overall thickness of the strained silicon layer is relatively thin, no additional CMP can be carried out for flattening out or smoothing the surface of the strained silicon layer to the desired values. In addition to the increasing the thickness to allow partial improvement in surface roughness, US2003/0215990 also proposes to control the temperature at which the layers are grown after planarization. Despite these improvements, final surface roughness values only on the order of 5 Å can be achieved.
Furthermore, the buried interface between the top layer, e.g., a strained layer, and the underlying layer have even a higher roughness, due to the heat treating and bake after CMP of the buffer layer. This buried interface, however, becomes a top free surface when the strained layer is transferred onto another substrate, such as a handle substrate to create a strained silicon on insulator type semiconductor heterostructure. This can, for example, be achieved using the well known SMART-CUT® layer cleaving process. Again also here, no additional CMP can be carried out for flattening out the surface due to its relatively thin thickness.
Surface roughness is critical for substrate quality, because a rough surface on the heterostructure will in turn lead to a rough final structure for the electronic devices that are to be developed thereon. A rough surface is also detrimental for the electrical behavior of the formed devices. It is therefore necessary to improve surface smoothness on such substrates to avoid or at lease minimize these problems.